As one of standard signal generators, there is a frequency synthesizer to which a PLL (Phase Locked Loop) is applied. In Patent Document 1, there has been described a frequency synthesizer that frequency-divides, analog/digital (A/D) converts, and quadranture-detects a frequency signal from a voltage controlled oscillating unit, and extracts a rotation vector rotating at a frequency difference between the frequency signal used for the detection and the (A/D) converted frequency signal, and integrates a signal corresponding to a difference between a frequency of the above rotation vector and a set frequency to set an integration result as a control voltage to the voltage controlled oscillating unit to thereby establish a PLL loop. In the above method, in order to stop the above-described rotation vector, the rotation vector is multiplied by a reverse rotation vector reversely rotating at a frequency determined in rough increments according to the set frequency to reduce a velocity of the vector, and a phase difference between the vectors whose velocities are reduced in each sampling time is detected, and the above phase difference is assumed to be the velocity of the vector, and the loop is operated so that the phase difference becomes zero.
The above frequency synthesizer has been used in a base station, a relay station, and the like, and when a PLL lock is unlocked to be in an unlock state, a countermeasure such that the frequency synthesizer is quickly switched to a system on a redundant side is required. Thus, in Patent Document 1, the frequency synthesizer is designed so as to monitor a scalar quantity of the vector whose velocity is reduced, and compare the above scalar quantity and a desired value determined in advance, and multiply an output of an A/D converter by a correction gain signal corresponding to a difference between the scalar quantity and the desired value, and correct a gain of the output signal to thereby suppress the above-described scalar quantity to a predetermined value. Then, the frequency synthesizer is designed so as to output an unlock detection signal when the above-described scalar quantity or the above-described correction gain signal deviates from a set range determined in advance.
However, the change in an input level to the A/D converter is detected after an arithmetic operation step of the above-described rotation vector and a multiplication step of the reverse vector, and these detection operations are performed intermittently by a clock, and thereby the determination is delayed by the amount of time for the arithmetic operation of a digital signal, resulting that it has been difficult to say that a request for instantly detecting the unlock state is sufficiently satisfied.
[Patent Document 1] Japanese Patent Application Laid-open No. 2008-35483